| Item | Slot #1 | Slot #2 |
|---|
| Ram Type | DDR4 | Not Populated |
| Maximum Clock Speed (MHz) | 1502 (XMP) | |
| Maximum Transfer Speed (MHz) | DDR4-3003 | |
| Maximum Bandwidth (MB/s) | PC4-24000 | |
| Memory Capacity (MB) | 8192 | |
| Jedec Manufacture Name | Crucial Technology | |
| Search Amazon.com | Search! | |
| SPD Revision | 1.1 | |
| Registered | No | |
| ECC | No | |
| On-Die ECC | No | |
| DIMM Slot # | 1 | |
| Manufactured | Week 29 of Year 2019 | |
| Module Part # | BLS8G4D30AESEK.M8FE | |
| Module Revision | 0x0 | |
| Module Serial # | 0xE25CA824 | |
| Module Manufacturing Location | 0 | |
| # of Row Addressing Bits | 16 | |
| # of Column Addressing Bits | 10 | |
| # of Banks | 16 | |
| # of Ranks | 1 | |
| Device Width in Bits | 8 | |
| Bus Width in Bits | 64 | |
| Module Voltage | 1.2V | |
| CAS Latencies Supported | 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 | |
| Timings @ Max Frequency (JEDEC) | 16-16-16-39 | |
| Maximum frequency (MHz) | 1200 | |
| Maximum Transfer Speed (MHz) | DDR4-2400 | |
| Maximum Bandwidth (MB/s) | PC4-19200 | |
| Minimum Clock Cycle Time, tCK (ns) | 0.833 | |
| Minimum CAS Latency Time, tAA (ns) | 13.320 | |
| Minimum RAS to CAS Delay, tRCD (ns) | 13.320 | |
| Minimum Row Precharge Time, tRP (ns) | 13.320 | |
| Minimum Active to Precharge Time, tRAS (ns) | 32.000 | |
| Minimum Row Active to Row Active Delay, tRRD (ns) | 3.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 45.320 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 350.000 | |
| | | |
| DDR4 Specific SPD Attributes | | |
| Maximum Clock Cycle Time, tCKmax (ns) | 1.600 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC2 (ns) | 260.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC4 (ns) | 160.000 | |
| Minimum Activate to Activate Delay Time different bank group, tRRD_Smin (ns) | 3.000 | |
| Minimum Activate to Activate Delay Time same bank group, tRRD_Lmin (ns) | 4.900 | |
| Minimum CAS to CAS Delay Time same bank group, tCCD_Lmin (ns) | 5.000 | |
| Minimum Four Activate Window Delay (ns) | 21.000 | |
| Maximum Activate Window in units of tREFI | 8192 | |
| Thermal Sensor Present | No | |
| DRAM Stepping | 0 | |
| DRAM Manufacture | Micron Technology | |
| SDRAM Package Type | Monolithic, 1 die, Single load stack | |
| Maximum Activate Count (MAC) | Unlimited MAC | |
| Post Package Repair Supported | No | |
| Module Type | UDIMM | |
| Module Height (mm) | 32 | |
| Module Thickness (front), (mm) | 2 | |
| Module Thickness (back), (mm) | 2 | |
| Reference Raw Card Used | Raw Card A Rev. 18 | |
| | | |
| XMP Attributes | | |
| XMP Revision | 2.0 | |
| Enthusiast / Certified Profile | | |
| Module voltage | 1.35V | |
| Clock speed (MHz) | 1502 | |
| Transfer Speed (MHz) | DDR4-3003 | |
| Bandwidth (MB/s) | PC4-24000 | |
| Minimum clock cycle time, tCK (ns) | 0.666 | |
| Supported CAS latencies | 7 8 9 10 11 12 13 14 15 16 17 18 19 20 | |
| Minimum CAS latency time, tAA (ns) | 9.875 | |
| Minimum RAS to CAS delay time, tRCD (ns) | 10.625 | |
| Minimum row precharge time, tRP (ns) | 10.625 | |
| Minimum active to precharge time, tRAS (ns) | 23.250 | |
| Supported timing at highest clock speed | 15-16-16-35 | |
| Minimum Active to Auto-Refresh Delay, tRC (ns) | 45.375 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC1 (ns) | 350.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC2 (ns) | 260.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC4 (ns) | 160.000 | |
| Minimum Four Activate Window Delay, tFAW (ns) | 21.000 | |
| Minimum Activate to Activate Delay Time different bank group, tRRD_S (ns) | 3.000 | |
| Minimum Activate to Activate Delay Time same bank group, tRRD_L (ns) | 4.900 | |
